1. Field of the Invention
This invention is related to the field of processors and, more particularly, to caching structures in processors.
2. Description of the Related Art
Processors typically implement virtual addressing, and also typically implement caches for storing recently accessed data and/or instructions. Typically, the processor generates a virtual address of a location to be accessed (i.e. read or written), and the virtual address is translated to a physical address to determine if the access hits in the cache. More particularly, the cache access is typically started in parallel with the translation, and the translation is used to detect if the cache access is a hit.
The cache access is typically one of the critical timing paths in the processor, and cache latency is also typically critical to the performance level achievable by the processor. Accordingly, processor designers often attempt to optimize their cache/translation designs to reduce cache latency and to meet timing requirements. However, many of the optimization techniques may increase the power consumption of the cache/translation circuitry. In many processors, the cache/translation circuitry may be one of the largest contributors to the overall power consumption of the processor.
As power consumption in processors has increased over time, the importance of controlling processor power consumption (and designing processors for reduced power consumption) has increased. Since the cache/translation circuitry is often a major contributor to power consumption of a processor, techniques for reducing power consumption in the cache/translation circuitry have become even more desirable.
To improve performance, set associative caches are often implemented in processors. In a set associative cache, a given address indexing into the cache selects a set of two or more cache line storage locations which may be used to store the cache line indicated by that address. The cache line storage locations in the set are referred to as the ways of the set, and a cache having W ways is referred to as W-way set associative (where W is an integer greater than one). Set associative caches typically have higher hit rates than direct-mapped caches of the same size, and thus may provide higher performance than direct-mapped caches. However, conventional set associative caches may also typically consume more power than direct-mapped caches of the same size. Generally, the cache includes a data memory storing the cached data and a tag memory storing a tag identifying the address of the cached data.
In a conventional set associative cache, each way of the data memory and the tag memory is accessed in response to an input address. The tags corresponding to each way in the set may be compared to determine which way is hit by the address (if any), and the data from the corresponding way is selected for output by the cache. Thus, each way of the data memory and the tag memory may be accessed, consuming power. Furthermore, since the cache access is often a critical timing path, the tag memory and data memory access may be optimized for timing and latency, which further increase power consumption. Still further, the caches are typically tagged with the physical address, and thus the translation circuitry is also typically in the critical path and thus optimized for timing and latency, which may increase power consumption in the translation circuitry.